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KB3511
System-Power
High Efficiency, Low Noise, Fast Transient Dual 800mA, 2.2MHz Step-Down DC/DC Converter
FEATURES

DESCRIPTION
The KB3511 is a high efficiency monolithic synchronous buck regulator using a constant frequency, current mode architecture. The device is available in an adjustable version and fixed output voltages of 1.8V and 3.3V. Supply current during operation is only 25A and drops to 1A in shutdown. The 2.5V to 6.5V input voltage range makes the KB3511 ideally suited for single Li-Ion battery-powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. Automatic Trickle Mode operation increases efficiency at light loads, further extending battery life. Switching frequency is internally set at 2.2MHz, allowing the use of small surface mount inductors and capacitors. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. Low output voltages are easily supported with the 0.6V feedback reference voltage. The KB3511 is available in a low profile (0.8mm) DFN33-10 package.
Up to 97% Efficiency 25uA No Load Current Per Channel 800mA Output Current 2.5V to 6.5V Input Voltage Range 2.2MHz Constant Frequency Operation No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle 0.6V Reference Allows Low Output Voltages Shutdown Mode Draws 1A Supply Current Current Mode Operation for Excellent Line and Load Transient Response Overtemperature Protected DFN33-10 Package
APPLICATIONS

Cellular Telephones Personal Information Appliances Wireless and DSL Modems Digital Still Cameras MP3 Players Portable Instruments
TYPICAL APPLICATION
KB3511 Efficiency Curve
VIN = 3.6V TO 6.0V C6
100
VIN=3.6V
*10 F *
Vin>4.5V Used
R1
C1 4.7F RESET L2 2.2H C5, 22pF
2
RUN1
3
VIN
9
RUN2 POR
R5 100k
95
RESET
EFFICIENCY (%)
3.3V 1.8V
6
*1
MODE/SYNC
8
L1 2.2H
90 85 80 75 70
KB3511A
VOUT2 = 3.3V AT 800mA
4 SW1 DFN3x3mm 1
VFB1 GND
SW2
7
C4, 22pF
VOUT1 = 1.8V AT 800mA
VFB2
10
R1 150k R2 300k C2 4.7F
C3 4.7F
R4 680k
65 60 1 10 100 LOAD CURRENT (mA) 1000
R3 150k
11 5
C1, C2, C3: 4.7uF 6.3V 0603
L1, L2: EVERCOM SD11-2R2 (3x3x1.2mm)
Figure 1. 3.3V/1.8V at 800mA Step-Down Regulators 1.3mm Height Core Supply
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KB3511
Peak SW Sink and Source Current ........................ 1.3A Operating Temperature Range (Note 2) .. - 40C to 85C Junction Temperature (Note 3) ............................ 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage .................................. - 0.3V to 6.5V RUN, VFB Voltages ..................................... - 0.3V to VIN SW Voltage .................................. - 0.3V to (VIN + 0.3V) P-Channel Switch Source Current (DC) ............. 800mA N-Channel Switch Sink Current (DC) ................. 800mA
PACkAGE/ORDER INFORMATION
TOP VIEW VFB1 RUN1 VIN SW1 GND 1 2 3 4 5 11 10 VFB2 9 RUN2 8 POR 7 SW2 6 MODE/ SYNC VFB1 = VFB2 = 0.6V
ORDER PART NUMBER
VOUT1 1
TOP VIEW 10 VOUT2 9 RUN2 11 8 NC 7 SW2 6 MODE/ SYNC
ORDER PART NUMBER KB3511B
VOUT1 = 1.5V VOUT2 = 2.2V
KB3511A
RUN1 VIN SW1 GND
2 3 4 5
DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN EXPOSED PAD IS PGND (PIN 11) MUST BE CONNECTED TO GND
DD PART MARKING
DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN EXPOSED PAD IS PGND (PIN 11) MUST BE CONNECTED TO GND
DD PART MARKING
TJMAX = 125C, JA = 45C/W, JC = 10C/W
TJMAX = 125C, JA = 45C/W, JC = 10C/W
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 3.6V unless otherwise specified.
SYMBOL VIN IFB VFB VLINE REG VLOAD REG IS PARAMETER Operating Voltage Range Feedback Pin Input Current Feedback Voltage (Note 3) Reference Voltage Line Regulation Output Voltage Load Regulation Input DC Supply Current Active Mode Shutdown fOSC fSYNC ILIM RDS(ON) ISW(LKG) Oscillator Frequency Synchronization Frequency Peak Switch Current Limit Top Switch On-Resistance Bottom Switch On-Resistance Switch Leakage Current VIN = 3V, FBK = 0.5V, Duty Cycle <35% VIN = 3.6V (Note 6) VIN = 3.6V (Note 6) VIN = 5V, VRUN = 0V, VFB = 0V 0.85 VFB1 = VFB2 = 0.6V RUN = 0V, VIN = 5.5V, MODE/SYNC = 0V VFB = 0.6V
CONDITIONS

MIN 2.5 0.588 0.585
TYP
MAX 6.5 30
UNITS V nA V V %/V %
0C TA 85C -40C TA 85C VIN = 2.5V to 5.5V (Note 3) (Note 3)
0.6 0.6 0.3 0.5 50 0.1
0.612 0.612 0.5
100 1 2.8 1.25 0.45 0.45 1
A A MHz MHz A A
1.6
2.2 2.2 1 0.35 0.30 0.01
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KB3511
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 3.6V unless otherwise specified.
SYMBOL POR PARAMETER Power-On Reset Threshold Power-On Reset On-Resistance Power-On Reset Delay VRUN IRUN RUN Threshold High RUN Leakage Current

CONDITIONS VFB Ramping Up, MODE/SYNC = 0V VFB Ramping Down, MODE/SYNC = 0V
MIN
TYP 8.5 -8.5 100 262,144
MAX
UNITS % %
200 1.5 1
Cycles V A
0.3
1 0.01
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The KB3511 is guaranteed to meet specified performance from 0C to 70C. Specifications over the - 40C and 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The KB3511 is tested in a proprietary test mode that connects
VFB to the output of the error amplifier. Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: TJ is calculated from the ambient TA and power dissipation PD according to the following formula: TJ = TA + (PD * JA). Note 6: The DFN switch on-resistance is guaranteed by correlation to wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS
Trickle Mode Operation
SW 5V/DIV SW 5V/DIV
PWM Mode
VOUT 200mV/DIV
Load Step
VOUT 100mV/DIV IL 200mA/DIV
VOUT 10mV/DIV IL 200mA/DIV
IL 500mA/DIV ILOAD 500mA/DIV
VIN = 3.6V 4s/DIV VOUT = 1.8V ILOAD = 50mA CIRCUIT OF FIGURE 1
VIN = 3.6V 1s/DIV VOUT = 1.8V ILOAD = 50mA CIRCUIT OF FIGURE 1
VIN = 3.6V 20s/DIV VOUT = 1.8V ILOAD = 50mA TO 600mA CIRCUIT OF FIGURE 1
Efficiency vs Input Voltage
100 TA = 25C 100mA
FREQUENCY (MHz)
Oscillator Frequency vs Temperature
1.70
OSCILLATOR FREQUENCY (MHz)
Oscillator Frequency vs Supply Voltage
1.8 TA = 25C 1.7 1.6 1.5 1.4 1.3 1.2
95 90
EFFICIENCY (%)
1.65 10mA 1.60 1.55 1.50 1.45 1.40 1.35 6 1.30 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125
1mA 85 80 75 70 600mA
65 VOUT = 1.8V CIRCUIT OF FIGURE 1 60 4 5 2 3 INPUT VOLTAGE (V)
2
3
4 SUPPLY VOLTAGE (V)
5
6
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KB3511
TYPICAL PERFORMANCE CHARACTERISTICS
Reference Voltage vs Temperature
0.615 VIN = 3.6V 0.610 REFERENCE VOLTAGE (V) 0.605 0.600 0.595 0.590 0.585 -50 -25 500 TA = 25C 450 450 RDS(ON) (m) RDS(ON) (m) 400 350 300 250 200 50 25 75 0 TEMPERATURE (C) 100 125 1 2 SYNCHRONOUS SWITCH MAIN SWITCH 400 350 300 250 200 150 3 4 VIN (V) 5 6 7 100 -50 -25 MAIN SWITCH SYNCHRONOUS SWITCH 0 25 50 75 100 125 150 TEMPERATURE (C)
RDS(ON) vs Input Voltage
550 500
RDS(ON) vs Temperature
VIN = 2.7V VIN = 4.2V VIN = 3.6V
Efficiency vs Load Current
100 3.6V 95 90 EFFICIENCY (%) 85 80 75 70 65 60 1 VOUT = 3.3V Trickle Mode OPERATION CIRCUIT OF FIGURE 1 10 100 LOAD CURRENT (mA) 1000 4.2V EFFICIENCY (%) 3.8V 95 100
Efficiency vs Load Current
4 Trickle Mode OPERATION 90 85 80 PWM MODE 75 70 65 60 1 VIN = 3.6V, VOUT = 1.8V NO LOAD ON OTHER CHANNEL 10 100 LOAD CURRENT (mA) 1000 VOUT ERROR (%)
Load Regulation
3 Trickle Mode OPERATION 2 1 0 PWM MODE -1 -2 -3 -4 1 VIN = 3.6V, VOUT = 1.8V NO LOAD ON OTHER CHANNEL 10 100 LOAD CURRENT (mA) 1000
Efficiency vs Load Current
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 1 VOUT = 1.2V Trickle Mode OPERATION CIRCUIT OF FIGURE 1 10 100 LOAD CURRENT (mA) 1000 4.2V EFFICIENCY (%) 3.3V 2.7V 100 95
Efficiency vs Load Current
0.5 0.4 3.3V 90 85 80 75 70 65 60 1 VOUT = 1.5V Trickle Mode OPERATION CIRCUIT OF FIGURE 1 10 100 LOAD CURRENT (mA) 1000 4.2V VOUT ERROR (%) 2.7V 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
Line Regulation
VOUT = 1.8V IOUT = 200mA TA = 25C
2
3
4 VIN (V)
5
6
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KB3511
be syncronized to an external oscillator applied to this pin and pulse skipping mode is automatically selected. SW2 (Pin 7): Regulator 2 Switch Node Connection to the Inductor. This pin swings from VIN to GND. POR (Pin 8): Power-On Reset . This common-drain logic output is pulled to GND when the output voltage is not within 8.5% of regulation and goes high after 175ms when both channels are within regulation. RUN2 (Pin 9): Output Feedback. Forcing this pin to VIN enables regulator 2, while forcing it to GND causes regulator 2 to shut down. VFB2 (Pin 10): Output Feedback. Receives the feedback voltage from the external resistive divider across the output. Nominal voltage for this pin is 0.6V. Exposed Pad (GND) (Pin 11): Power Ground. Connect to the (-) terminal of COUT, and (-) terminal of CIN. Must be soldered to electrical ground on PCB.
PIN FUNCTIONS
VFB1 (Pin 1): Output Feedback. Receives the feedback voltage from the external resistive divider across the output. Nominal voltage for this pin is 0.6V. RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to VIN enables regulator 1, while forcing it to GND causes regulator 1 to shut down. VIN (Pin 3): Main Power Supply. Must be closely decoupled to GND. SW1 (Pin 4): Regulator 1 Switch Node Connection to the Inductor. This pin swings from VIN to GND. GND (Pin 5): Main Ground. Connect to the (-) terminal of COUT, and (-) terminal of CIN. MODE/SYNC (Pin 6): Combination Mode Selection and Oscillator Synchronization. This pin controls the operation of the device. When tied to VIN or GND, Trickle Mode operation or PWM mode is selected, respectively. Do not float this pin. The oscillation frequency can
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KB3511
Trickle Clamp VIN
SIMPLIFIED BLOC DIAGRAM
REGULATOR 1 MODE/SYNC 6 SLOPE COMP
0.6V
+
EA
-
ITH 0.35V
EN SLEEP
-
ICOMP
+
5
VFB1
1
-
+
Trickle S Q RS LATCH R Q SWITCHING LOGIC AND BLANKING CIRCUIT
0.55V
-
UVDET
UV
+
ANTI SHOOTTHRU 4 SW1
+
OVDET 0.65V OV
IRCMP
PGOOD1 RUN1 RUN2 2 0.6V REF 9 OSC PGOOD2 REGULATOR 2 (IDENTICAL TO REGULATOR 1) VFB2 10 OSC,2.2MHz POR COUNTER
OPERATION
The KB3511 uses a constant frequency, current mode architecture. The operating frequency is set at 2.2MHz and can be synchronized to an external oscillator. Both channels share the same clock and run in-phase. To suit a variety of applications, the selectable Mode pin allows the user to trade-off noise for efficiency. The output voltage is set by an external divider returned to the VFB pins. An error amplfier compares the divided output voltage with a reference voltage of 0.6V and adjusts the peak inductor current accordingly. Overvoltage and undervoltage comparators will pull the POR output low if the output voltage is not within 8.5%. The POR output will go high after 262,144 clock cycles (about 120ms) of achieving regulation. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle when the VFB voltage is below the the reference voltage. The current into the inductor and the load increases until the current limit is reached. The switch turns off and energy stored in the inductor flows through the bottom switch (N-channel MOSFET) into the load until the next clock cycle. The peak inductor current is controlled by the internally compensated ITH voltage, which is the output of the error amplifier.This amplifier compares the VFB pin to the 0.6V reference. When the load current increases, the VFB voltage decreases slightly below the reference. This
6
-
SHUTDOWN
+
11 GND VIN 3 VIN 8 POR 5 GND 7 SW2
-
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KB3511
For lower ripple noise at low currents, the pulse skipping mode can be used. In this mode, the KB3511 continues to switch at a constant frequency down to very low currents, where it will begin skipping pulses. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. In dropout, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel MOSFET and the inductor. An important design consideration is that the RDS(ON) of the P-channel switch increases with decreasing input supply voltage (See Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the KB3511 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information Section). Low Supply Operation The KB3511 incorporates an Under-Voltage Lockout circuit which shuts down the part when the input voltage drops below about 1.65V to prevent unstable operation.
OPERATION
decrease causes the error amplifier to increase the ITH voltage until the average inductor current matches the new load current. The main control loop is shut down by pulling the RUN pin to ground. Low Current Operation Two modes are available to control the operation of the KB3511 at low currents. Both modes automatically switch from continuous operation to to the selected mode when the load current is low. To optimize efficiency, the Trickle Mode operation can be selected. When the load is relatively light, the KB3511 automatically switches into Trickle Mode operation in which the PMOS switch operates intermittently based on load demand with a fixed peak inductor current. By running cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs are minimized. The main control loop is interrupted when the output voltage reaches the desired regulated value. A hysteretic voltage comparator trips when ITH is below 0.28V, shutting off the switch and reducing the power. The output capacitor and the inductor supply the power to the load until ITH/RUN exceeds 0.6V, turning on the switch and the main control loop which starts another cycle.
APPLICATIONS INFORMATION
A general KB3511 application circuit is shown in Figure 2. External component selection is driven by the load requirement, and begins with the selection of the inductor L. Once the inductor is chosen, CIN and COUT can be selected. Inductor Selection Although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. The inductor ripple current IL decreases with higher inductance and increases with higher VIN or VOUT:
V V IL = OUT 1 OUT fO L VIN Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability. A reasonable starting point for setting ripple current is IL = 0.3 * ILIM, where ILIM is the peak switch current limit. The largest ripple current IL occurs at the maximum input voltage. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation:
L= VOUT VOUT 1 fO IL VIN(MAX)
The inductor value will also have an effect on Trickle Mode operation. The transition from low current operation begins when the peak inductor current falls below a level set by the Trickle clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load
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APPLICATIONS INFORMATION
currents. This causes a dip in efficiency in the upper range Table 1. Representative Surface Mount Inductors VALUE DCR MAX DC SIZE of low current operation. In Trickle Mode operation, lower PART NUMBER (H) ( MAX) CURRENT (A) W x L x H (mm3) inductance values will cause the Trickle frequency to inEVERCOM 1.5 0.043 0.95 3.0 x 3.0 x 1.2 crease.
SD11
Inductor Core Selection Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characterisitics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the KB3511 requires to operate. Table 1 shows some typical surface mount inductors that work well in KB3511 applications. Input Capacitor (CIN) Selection In continuous mode, the input current of the converter is a square wave with a duty cycle of approximately VOUT/ VIN. To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:
2.2 3.3 4.7
0.075 0.110 0.162
0.80 0.70 0.60
Sumida CMD4D06 Panasonic ELT5KT Murata LQH32CN
2.2 3.3 4.7 3.3 4.7 1.0 2.2 4.7
0.116 0.174 0.216 0.17 0.20 0.060 0.097 0.150
0.950 0.770 0.750 1.00 0.95 1.00 0.79 0.65
3.5 x 4.3 x 0.8
4.5 x 5.4 x 1.2 2.5 x 3.2 x 2.0
Output Capacitor (COUT) Selection The selection of COUT is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (VOUT) is determined by:
1 VOUT IL ESR + 8fO C OUT
VOUT (VIN VOUT ) VIN where the maximum average output current IMAX equals the peak current minus half the peak-to-peak ripple current, IMAX = ILIM - IL/2. IRMS IMAX
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case is commonly used to design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 0.1F to 1F ceramic capacitor is also recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution.
where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since IL increases with input voltage. With IL = 0.3 * ILIM the output ripple will be less than 100mV at maximum VIN and fO = 2.2MHz with: ESRCOUT < 150m Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantulum capacitors are all available in surface mount packages. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any aluminum electrolytic at a somewhat higher price. Special polymer
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Also, ceramic caps are prone to temperature effects which requires the designer to check loop stability over the operating temperature range. To minimize their large temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. A good selection of ceramic capacitors is available from Taiyo Yuden, TDK, and Murata. Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, 3-4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 3 times the linear drop of the first cycle. Thus, a good place to start is with the output capacitor size of approximately:
APPLICATIONS INFORMATION
capacitors, such as Sanyo POSCAP, offer very low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but it has a larger ESR and it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and are often used in extremely costsensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have the lowest ESR and cost, but also have the lowest capacitance density, a high voltage and temperature coefficient, and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. Other capacitor types include the Panasonic Special Polymer (SP) capacitors. In most cases, 0.1F to 1F of ceramic capacitors should also be placed close to the KB3511 in parallel with the main capacitors for high frequency decoupling.
VIN = 2.5V TO 5.5V CIN Trickle* PWM* L2 VOUT1 C5 SW1 SW2 C4 RUN2 VIN RUN1 POR R5 POWER-ON RESET L1 VOUT2
MODE/SYNC KB3511ADJ
R4 COUT2 R3
VFB2 GND
VFB2 R2 R1 COUT1
*MODE/SYNC = 0V: PWM MODE/SYNC = VIN: Trickle Mode
COUT 3
IOUT fO VDROOP
Figure 2. KB3511 General Schematic
More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 10F ceramic capacitor is usually enough for these conditions. Setting the Output Voltage The KB3511 develops a 0.6V reference voltage between the feedback pin, VFB, and the ground as shown in Figure 2. The output voltage is set by a resistive divider according to the following formula:
Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low ESR. Unfortunately, the ESR is so low that it can cause loop stability problems. Solid tantalum capacitor ESR generates a loop "zero" at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually resonate with their ESL before ESR becomes effective.
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Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD * ESR, where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem.
APPLICATIONS INFORMATION
VOUT R2 = 0.6V 1 + R1
Keeping the current small (<5A) in these resistors maximizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. To improve the frequency response, a feed-forward capacitor CF may also be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Power-On Reset
The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard secondThe POR pin is an open-drain output which pulls low when order overshoot/DC ratio cannot be used to determine either regulator is out of regulation. When both output phase margin. In addition, a feed-forward capacitor, C F, voltages are within 8.5% of regulation, a timer is started can be added to improve the high frequency response, as which releases POR after 218 clock cycles (about 120ms). shown in Figure 2. Capacitor CF provides phase lead by This delay can be significantly longer in Trickle Mode creating a high frequency zero with R2 which improves the operation with low load currents, since the clock cycles phase margin. only occur during a Trickle and there could be milliseconds of time between Trickles. This can be bypassed by tying the The output voltage settling behavior is related to the POR output to the MODE/SYNC input, to force pulse stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed PWM mode during a reset. In addition, if the output voltage faults during Trickle Mode sleep, POR could have a explanation of optimizing the compensation components, slight delay for an undervoltage output condition and may including a review of control loop theory, refer to Applicanot respond to an overvoltage output. This can be avoided tion Note 76. by using pulse skipping mode instead. When either chan- In some applications, a more severe transient can be nel is shut down, the POR output is pulled low, since one caused by switching in loads with large (>1F) input or both of the channels are not in regulation. capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No Mode Selection & Frequency Synchronization regulator can deliver enough current to prevent this probThe MODE/SYNC pin is a multipurpose pin which provides lem, if the switch connecting the load has low resistance mode selection and frequency synchronization. Connect- and is driven quickly. The solution is to limit the turn-on ing this pin to VIN enables Trickle Mode operation, which speed of the load switch driver. A Hot Swap controller is provides the best low current efficiency at the cost of a designed specifically for this purpose and usually incorpohigher output voltage ripple. When this pin is connected to rates current limiting, short-circuit protection, and softstarting. ground, PWM operation is selected which provides the lowest output ripple, at the cost of low current Efficiency Considerations efficiency. The percent efficiency of a switching regulator is equal to The KB3511 can also be synchronized to an external 2.2MHz clock signal by the MODE/SYNC pin. During the output power divided by the input power times 100%. synchronization, the mode is set to pulse skipping and the It is often useful to analyze individual losses to determine top switch turn-on is synchronized to the rising edge of the what is limiting the efficiency and which change would external clock.
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KB3511
degradations in portable systems. It is very important to include these "system" level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In a majority of applications, the KB3511 does not dissipate much heat due to its high efficiency. However, in applications where the KB3511 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance. To prevent the KB3511 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD * JA where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the KB3511 is in dropout on both channels at an input voltage of 2.7V with a load current of 800mA and an ambient temperature of 70C. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the main switch is 0.425. Therefore, power dissipated by each channel is: PD = I2 * RDS(ON) = 272mW The MS package junction-to-ambient thermal resistance, JA, is 45C/W. Therefore, the junction temperature of the
APPLICATIONS INFORMATION
produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, 4 main sources usually account for most of the losses in KB3511 circuits: 1)V IN quiescent current, 2) switching losses, 3) I2R losses, 4) other losses. 1) The VIN current is the DC supply current given in the Electrical Characteristics which excludes MOSFET driver and control currents. VIN current results in a small (<0.1%) loss that increases with VIN, even at no load. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 3) I2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flowing through inductor L, but is "chopped" between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 4) Other `hidden' losses such as copper trace and internal battery resistances can account for additional efficiency
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Kingbor Technology Co.,Ltd
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KB3511
Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the KB3511. These items are also illustrated graphically in the layout diagram of Figure 3. Check the following in your layout: 1. Does the capacitor CIN connect to the power VIN (Pin 3) and GND (exposed pad) as close as possible? This capacitor provides the AC current to the internal power MOSFETs and their drivers. 2. Are the COUT and L1 closely connected? The (-) plate of COUT returns current to GND and the (-) plate of CIN. 3. The resistor divider, R1 and R2, must be connected between the (+) plate of COUT and a ground sense line terminated near GND (exposed pad). The feedback signals VFB should be routed away from noisy components and traces, such as the SW line (Pins 4 and 7), and its trace should be minimized. 4. Keep sensitive components away from the SW pins. The input capacitor CIN and the resistors R1 to R4 should be routed away from the SW traces and the inductors. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the GND pin at one point and should not share the high current path of CIN or COUT. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to VIN or GND.
VIN CIN RUN2 VIN RUN1 POR
APPLICATIONS INFORMATION
regulator operating in a 70C ambient temperature is approximately: TJ = 2 * 0.272 * 45 + 70 = 95C which is below the absolute maximum junction temperature of 125C. Design Example As a design example, consider using the KB3511 in an portable application with a Li-Ion battery. The battery provides a VIN = 3.6V to 4.2V. The load requires a maximum of 600mA in active mode and 2mA in standby mode. The output voltage is VOUT = 3.3V. Since the load still needs power in standby, Trickle Mode operation is selected for good low load efficiency. First, calculate the inductor value for about 30% ripple current at maximum VIN:
L=
3.3V 3.3V 1 - = 1.07H 2.2MHz 300mA 4.2V
Choosing the closest inductor from a vendor of 1.0H inductor, results in a maximum ripple current of:
IL = 3.3V 3.3V 1- = 330mA 2.2MHz 1.0 4.2V
For cost reasons, a ceramic capacitor will be used. COUT selection is then based on load step droop instead of ESR requirements. For a 5% output droop:
COUT 3
600mA = 4.9F 2.2MHz (5% 3.3V)
The closest standard value is 10F. Since the output impedance of a Li-Ion battery is very low, CIN is typically 10F. The output voltage can now be programmed by choosing the values of R1 and R2. To maintain high efficiency, the current in these resistors should be kept small. Choosing 2A with the 0.6V feedback voltage makes R1~300k. A close standard 1% resistor is 280k, and R2 is then 887k. The PGOOD pin is a common drain output and requires a pull-up resistor. A 100k resistor is used for adequate speed. Figure 1 shows the complete schematic for this design example.
MODE/SYNC KB3511ADJ L2 VOUT1 C5 SW1
L1 SW2 C4 VOUT2
R4 COUT2 R3
VFB1 GND
VFB2 R2 R1 COUT1
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 3. KB3511 Layout Diagram (See Board Layout Checklist)
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Kingbor Technology Co.,Ltd
TEL:(86)0755-26508846 FAX:(86)0755-26509052
KB3511
APPLICATIONS INFORMATION TYPICAL APPLICATION
Low Ripple Buck Regulators Using Ceramic Capacitors
VIN = 3.6V TO 6.0V C1 4.7F RESET L2 2.2H C5, 22pF
2
RUN1
3
VIN
9
RUN2 POR
R5 100k
6
MODE/SYNC
8
L1 2.2H
RESET
KB3511A
VOUT2 = 3.3V AT 800mA
4 SW1 DFN3x3mm 1
VFB1 GND
SW2
7
C4, 22pF
VOUT1 = 1.8V AT 800mA
VFB2
10
R2 R1 300k 150k C2 4.7F
C3 4.7F
R4 680k
R3 150k
11 5
C1, C2, C3: 4.7uF 6.3V 0603
L1, L2: EVERCOM SD11-2R2 (3x3x1.2mm)
KB3511 Efficiency Curve
100 95 90
EFFICIENCY (%)
VIN=3.6V
3.3V 1.8V
85 80 75 70 65 60 1 10 100 LOAD CURRENT (mA) 1000
VOUT
91.5%
91.5%
120ms RESET
120ms
Reset Timing Diagram
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Kingbor Technology Co.,Ltd
TEL:(86)0755-26508846 FAX:(86)0755-26509052
KB3511
PACAGE DESCRIPTION
DD Package 10-Lead Plastic DFN (3mm x 3mm)
R = 0.115 TYP 6 0.675 0.05 10 0.38 0.10
3.50 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE KB WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE PIN 1 TOP MARK (SEE NOTE 5)
3.00 0.10 (4 SIDES)
1.65 0.10 (2 SIDES)
(DD10) DFN 0403
5 0.200 REF 0.75 0.05 2.38 0.10 (2 SIDES)
1
0.25 0.05 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD
4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Kingbor Technology
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